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Starting with the Cortex-A75, this CPU is more inspired by the Cortex-A73 rather than a direct upgrade of it. ARM states that there’s been a much larger number of micro-architecture changes this time around compared to the introduction of the A73, or even the move from the A57 to the A72.
The result is that ARM has made performance improvements across the board, resulting in a typical 22 percent boost to single threaded performance over the Cortex-A73 on the same process node and running at the same frequency. More specifically, ARM quotes a 33 percent boost to floating point and NEON performance, while memory throughput sees at 16 percent boost.
Clock speed wise, the Corex-A75 is likely to top out at 3 GHz on 10 nm, but could be pushed a little higher on future 7 nm designs. ARM says that for the same workload, the A75 won’t consume any more power than the A73, but it can be pushed further if extra performance is required, at the expense of some extra energy consumption. Although in mobile implementations, we aren’t likely to see SoC manufacturers push the power consumption any higher than they already do.
ARM has accomplished these improvements via a number of major microarchitecture changes. The Cortex-A75 moves two a 3-way superscalar design, from 2-way in the Cortex-A73. What this means is that, given a specific workload, the Cortex-A75 is able to execute up to 3 instructions in parallel per clock cycle, essentially increasing the core’s maximum throughput. The A75 boasts 7 execution units, two load/stores, two NEON and FPU, a branch, and two integer cores.
Speaking of NEON, ARM has also introduced a dedicated renaming engine for NEON FPU instructions. There’s now support for FP16 half-precision processing, which offers double the throughput for limited resolution processing examples, such as image processing. There’s also support for the Int8 dot product number format too, which offers a boost to a number of neural network algorithms.
To help keep the processor’s out-of-order pipeline well fed, ARM has adopted 4-wide instruction fetching to grab four instructions per cycle. The processor is now also able to perform single cycle decode with instruction fusing and micro-ops too. The core’s branch predictor has also been given a tune-up to keep up with the wider out-of-order execution capabilities of the A75. However, it’s still based on the same 0-cycle design as the A73, which uses a large Branch Target Address Cache (BTAC) and Micro-BTAC.
Finally, the Cortex-A75 now features a private L2 cache, implementable as either 256KB or 512KB, with a shared L3 cache available when implementing a DynamIQ multi-core solution, and most of the data in these caches will be exclusive. This change results in a much lower latency for hitting the L2 cache, down from 20 cycles with the Cortex-A73 to just 11 cycles in the A75.
Put simply, all of this means that ARM is not only boosting the performance of the A75 by allowing for additional instructions to be executed in a single cycle, but has also designed a micro-architecture better capable of keeping the core fed with instructions. As we mentioned in our overview of DynamIQ, the Cortex-A75 also implements the new DynamIQ Shared Unit as part of its design. This introduces new cache stashing, low latency access to peripherals, and fine-grain power management options into the core as well.
Cortex-A55The Cortex-A55 represents a notable but less drastic overhaul to ARM’s power efficient processor design, with a number of important changes from last generation’s hugely popular Cortex-A53 core. Energy efficiency remains a top priority with this tier of ARM CPUs, and the A55 boasts a 15 percent improvement to power efficiency over the A53. At the same time, ARM has been able to boost performance two fold in certain memory bound situations, with a typical 18 percent performance improvement over an A53 running at the same speeds and on the same process node.
Wrap UpOn their own, both the Cortex-A75 and Cortex-A55 offer notable improvements over the company’s last generation cores, both in terms of peak performance and energy efficiency. Even on current processing nodes, we can expect better single threaded performance and lower power drain for less demanding tasks than today’s A73/A53 big.LITTLE processors.
Of course, both of these new chips also mark the introduction of ARM’s DynamIQ multi-core technology, which further optimizes the balancing of power and performance that is so essential for mobile products. Not only that, but DynamIQ brings much more flexibility to the design table, and will empower particularly mid-range SoCs to eke out extra performance with very few extra costs. Backed up by the individual improvements brought to the A75 and A55, this is looking like a potent combination for future smartphones.
We most likely won’t see any mobile products featuring these new CPU cores arrive on the market until early 2023, but we may see SoC announcements based around these products as early as the closing quarter of this year.
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